Speedy and accurate image super‐resolution via deeply recursive CNN with skip connection and network in network. Issue 7 (7th May 2019)

• Record Type: Journal Article
• Authors: Guo, Dan; Niu, Yanxiong; Xie, Pengyan
• Is Part Of: IET image processing. Volume 13:Issue 7(2019)
• Page Start: 1201
• Page End: 1209
• Publication Date: 2019-05-07
• Subjects: neural nets -- learning (artificial intelligence) -- image resolution -- feature extraction -- convolution -- image reconstruction; accurate image super‐resolution -- deeply recursive CNN -- skip connection -- single image super‐resolution methods -- deep convolutional neural network -- on‐chip devices -- novel SISR method -- network structure -- image feature extraction -- parallelised 1 × 1 CNNs -- image reconstruction -- recursive learning -- state‐of‐the‐art methods; Image processing -- Periodicals; 621.36705
• DOI: 10.1049/iet-ipr.2018.5907
• Languages: English
• ISSNs: 1751-9659

Abstract

Abstract : The single image super‐resolution (SISR) methods based on the deep convolutional neural network (CNN) have recently achieved significant improvements in accuracy, advancing the state of the art. However, these deeper models are computationally expensive and require a large number of parameters. Accordingly, they demand more memory and are unsuitable for on‐chip devices. In this study, a novel SISR method using a deeply recursive CNN with skip connections and a network in network structure is proposed. The deeply recursive CNN with skip connections is adopted for the image feature extraction at both local and global levels. Parallelised 1 × 1 CNNs, usually called a network in network structure, are adopted for image reconstruction. Specifically, recursive learning is utilised to control the number of model parameters needed and residual learning is used to ease the difficulty of training. The proposed method performs favourably against the state‐of‐the‐art methods in terms of computational speed and accuracy. It significantly outperforms the previous methods by a large margin, while demanding far fewer parameters. This model requires less memory and is friendly to on‐chip devices.