Low‐latency median filter core for hardware implementation of 5 × 5 median filtering. Issue 10 (14th September 2017)

• Record Type: Journal Article
• Authors: Kumar, Vineet; Asati, Abhijit; Gupta, Anu
• Is Part Of: IET image processing. Volume 11:Issue 10(2017)
• Page Start: 927
• Page End: 934
• Publication Date: 2017-09-14
• Subjects: median filters -- field programmable gate arrays -- UHF filters; low‐latency median filter core -- LLMF core architecture -- hardware implementation -- median filtering -- integer values -- Xilinx Zynq FPGA device -- reduced clock cycle latency -- frequency 394 MHz; Image processing -- Periodicals; 621.36705
• DOI: 10.1049/iet-ipr.2016.0737
• Languages: English
• ISSNs: 1751-9659

Abstract

Abstract : This study presents hardware implementation of 5 × 5 median filter that uses a new low‐latency median filter (LLMF) core in order to find the median of 25 integer values. The proposed LLMF core architecture computes the median of 25 integers in just three clock cycles. The maximum frequency of operation of the proposed median filter architecture is 394 MHz on the Xilinx Zynq FPGA device. The proposed LLMF core provides reduced clock cycle latency compared with the existing state‐of‐the‐art median filter core architectures.