Area‐efficient parallel adder with faithful approximation for image and signal processing applications. Issue 13 (15th October 2019)

• Record Type: Journal Article
• Authors: Palanisamy, Gnanambikai; Krishnasamy Natarajan, Vijeyakumar; Sundaram, Kalaiselvi
• Is Part Of: IET image processing. Volume 13:Issue 13(2019)
• Page Start: 2587
• Page End: 2594
• Publication Date: 2019-10-15
• Subjects: CMOS logic circuits -- logic design -- adders -- low‐power electronics -- approximation theory; faithful approximation -- transistor switching -- arithmetic operations -- n bit input -- m bit adder block -- exact logic -- carry select addition algorithm -- least significant approximate part -- unit bit value -- approximate blocks -- area‐efficient parallel adder -- EFA -- FTFA cells -- FTFA designs -- approximate logic -- carry by‐pass addition algorithm -- image processing applications -- area‐efficient portable complementary metal–oxide–semiconductor processor design -- low‐power complementary metal–oxide–semiconductor processor design -- signal processing application demand reduction -- least n‐2m blocks -- exact full adder -- error‐tolerant parallel adder cells -- Cadence Encounter -- ASIC technology -- size 90.0 nm; Image processing -- Periodicals; 621.36705
• DOI: 10.1049/iet-ipr.2019.0580
• Languages: English
• ISSNs: 1751-9659

Abstract

Abstract : Design of low‐power and area‐efficient portable complementary metal–oxide–semiconductor processors for image and signal processing applications demand reduction in transistor switching and count. Adder is the fundamental block of all arithmetic operations performed in processing units. In this study, an error‐tolerant parallel adder with faithful approximation is proposed that can optimise area and accuracy. In the proposed parallel adder, for n bit input and m bit adder block, least n /2 m blocks are designed with approximate logic using carry by‐pass addition algorithm and most n /2 m blocks are designed with exact logic using carry select addition algorithm. Least significant approximate part of the adder is designed with either exact full adder (EFA) or fault‐tolerant full adder (FTFA) cells. This confines the maximum error in the proposed‐EFA and proposed‐FTFA designs to be not more than unit bit value with weights 2 [( n /2 m )−1] m and 2 n /2, respectively. Two different FTFA cells are proposed and implemented in the approximate blocks. The synthesis results of the proposed‐EFA, proposed‐FTFA1 and proposed‐FTFA2 designs using Cadence Encounter with 90 nm ASIC technology for n = 16, m = 4 demonstrated an area saving of 22.3, 28.2 and 35%, respectively, when compared to the conventional counterpart.