Area‐delay‐power‐efficient architecture for folded two‐dimensional discrete wavelet transform by multiple lifting computation. Issue 6 (1st June 2014)

• Record Type: Journal Article
• Authors: Mohanty, Basant Kumar; Meher, Pramod K.
• Is Part Of: IET image processing. Volume 8:Issue 6(2014)
• Page Start: 345
• Page End: 353
• Publication Date: 2014-06-01
• Subjects: application specific integrated circuits -- data compression -- discrete wavelet transforms -- image coding -- microprocessor chips; area‐delay‐power‐efficient architecture -- folded 2D discrete wavelet transform -- multiple lifting computation -- block processing -- combined‐lifting approach -- separated‐lifting approach -- CLF -- SLF -- register requirements -- column processing -- scheduling scheme -- block‐based lifting 2D DWT computation -- parallel‐pipeline structure -- frame‐buffer size -- input block size -- 3N on‐chip memory words -- ASIC synthesis -- image compression; Image processing -- Periodicals; 621.36705
• DOI: 10.1049/iet-ipr.2012.0661
• Languages: English
• ISSNs: 1751-9659

Abstract

Abstract : Multiple lifting computation could be performed for block processing of two‐dimensional (2D) discrete wavelet transform (DWT) by combined‐lifting (CLF) or separated‐lifting (SLF) approaches. CLF and SLF have the same computational complexities but they differ by their register requirements. In this study, the authors have chosen CLF for row processing and SLF for column processing, and suggested an efficient scheduling scheme for the computation of block‐based lifting 2D DWT. Based on this approach, the authors have derived a parallel‐pipeline structure for high‐throughput implementation of one‐level lifting 2D DWT. The authors have partitioned the multilevel 2D DWT computation appropriately and mapped that to a folded structure where the frame‐buffer size is independent of input block size. The proposed structure requires 3 N on‐chip memory words, which is the lowest among all the existing similar structures. Compared with the best of the existing block‐based structures for the one‐level DWT, the proposed structure involves less on‐chip memory words, requires the same number of multipliers and adders and offers the same throughput rate. The application specific integrated circuit (ASIC) synthesis result shows that the proposed structure involves significantly less area‐delay‐product and less energy per image than those of the best of the available designs.