Double Negative Differential Transconductance Characteristic: From Device to Circuit Application toward Quaternary Inverter. (25th September 2019) - Lim, Ji‐Hye; Shim, Jaewoo; Kang, Beom‐Seok; Shin, Gicheol; Kim, Hyeongjun; Andreev, Maksim; Jung, Kil‐Su; Kim, Kwan‐Ho; Choi, Jae‐Woong; Lee, Yoonmyung; Park, Jin‐Hong
Abstract: Multi‐valued logic (MVL) computing, which uses more than three logical states, is a promising future technology for handling huge amounts of data in the forthcoming "big data" era. The feasibility of MVL computing depends on the development of new concept devices/circuits beyond the complementary metal oxide semiconductor (CMOS) technology. This is because many CMOS devices are required to implement basic MVL functions, such as multilevel NOT, AND, and OR. In this study, a novel MVL device is reported with a complementarily controllable potential well, featuring the negative differential transconductance (NDT) phenomenon. This NDT device implemented on the WS2 –graphene–WSe2 van der Waals heterostructure is evolved to a double‐NDT device operating on the basis of two consecutive NDT phenomena via structural engineering and parallel device configuration. This double‐NDT device is intensively analyzed via atomic force microscopy, kelvin probe force microscopy, Raman spectroscopy, and temperature‐dependent electrical measurement to gain a detailed understanding of its operating mechanism. Finally, the operation of a quaternary inverter configured with the double‐peak NDT device and a p‐channel transistor through Cadence circuit simulation is theoretically demonstrated. Abstract : The negative differential transconductance (NDT) device is implemented on the WS2 –graphene–WSe2 van der Waals heterostructure. This NDT device is then expanded to the double peak NDT device by connecting two different NDT devices (type‐1 and type‐2) in parallel. A quaternary inverter configured with a double peak NDT device and a p‐channel transistor operates with four stable logic states.