Analysis and design of a low jitter delay‐locked loop using lock state detector. (15th March 2021)

• Record Type: Journal Article
• Authors: Modanlou, Shahram; Ardeshir, Gholamreza; Gholami, Mohammad
• Is Part Of: International journal of circuit theory and applications. Volume 49:Number 5(2021)
• Page Start: 1410
• Page End: 1419
• Publication Date: 2021-03-15
• Subjects: CP -- DLL -- jitter -- PD -- VCDL; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2923
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V. Abstract : In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology.