Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis. Issue 1 (1st January 2015)

• Record Type: Journal Article
• Authors: He, Wei; Bhasin, Shivam; Otero, Andres; Graba, Tarik; de la Torre, Eduardo; Danger, Jean‐Luc
• Is Part Of: IET information security. Volume 9:Issue 1(2015)
• Page Start: 1
• Page End: 13
• Publication Date: 2015-01-01
• Subjects: coprocessors -- correlation theory -- cryptography -- electromagnetic fields -- field programmable gate arrays -- formal verification -- logic design -- logic gates -- network routing -- random‐access storage -- synchronisation; security verification -- side channel analysis -- dual rail precharge logic -- dual rail structure -- balanced cell‐based dual rail logic -- compound gate synchronisation -- global precharge signal -- differential power -- electromagnetic analyses -- fleld programmable gate array -- complementary nets -- routing repair technique -- routing effect -- AES coprocessor -- block RAM‐based BCDL -- Xilinx Virtex‐5 FPGA -- asymptotic correlation EM analyses -- consecutive routing scheme -- nonidentical routing -- mutual information analyses; Computer security -- Periodicals; Cryptography -- Periodicals; Computer networks -- Security measures -- Periodicals; Database security -- Periodicals; 005.8
• DOI: 10.1049/iet-ifs.2013.0058
• Languages: English
• ISSNs: 1751-8709

Abstract

Abstract : Conventional dual‐rail precharge logic suffers from difficult implementations of dual‐rail structure for obtaining strict compensation between the counterpart rails. As a light‐weight and high‐speed dual‐rail style, balanced cell‐based dual‐rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security‐sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)‐co‐processor is executed that is constructed on block random access memory (RAM)‐based BCDL in Xilinx Virtex‐5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non‐identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.