Template attack on SPA and FA resistant implementation of Montgomery ladder. Issue 5 (1st September 2016)

• Record Type: Journal Article
• Authors: Chakraborty, Abhishek; Bhattacharya, Sarani; Dixit, Tanu Hari; Rebeiro, Chester; Mukhopadhyay, Debdeep
• Is Part Of: IET information security. Volume 10:Issue 5(2016)
• Page Start: 245
• Page End: 251
• Publication Date: 2016-09-01
• Subjects: public key cryptography -- embedded systems -- least squares approximations -- cache storage; template attack -- FA resistant implementation -- SPA resistant implementation -- montgomery ladder -- hardware implementations -- Rivest‐Shamir‐Adleman algorithm -- RSA‐Chinese remainder theorem -- fault analysis attacks -- embedded devices -- smart cards -- RFID -- storage overheads -- CHES'02 -- simple power analysis attacks -- Joye countermeasure -- Xilinx Microblaze soft‐core processor -- SASEBO‐W standard side‐channel analysis board -- least squares support vector machine based binary classifiers -- power trace classification -- cache timing attacks -- spy process; Computer security -- Periodicals; Cryptography -- Periodicals; Computer networks -- Security measures -- Periodicals; Database security -- Periodicals; 005.8
• DOI: 10.1049/iet-ifs.2015.0399
• Languages: English
• ISSNs: 1751-8709

Abstract

Abstract : Hardware implementations of the well‐known Rivest–Shamir–Adleman (RSA) algorithm have been shown to be vulnerable to power and fault analysis (FA) attacks. To implement protected designs of RSA‐Chinese remainder theorem in embedded devices, like smart cards or RFIDs, the one needs to find solutions which require less computations as well as incurs low storage overheads. One such efficient scheme was proposed by Joye et al . in CHES'02 and it was claimed to be secure against both simple power analysis (SPA) and FA attacks. In this study, the authors demonstrate a template attack (TA) against Joye's countermeasure and show that the scheme can be broken with a low number of power traces. In addition, the authors report the experimental results of the proposed attack against an implementation of Joye's scheme on a Xilinx Microblaze soft‐core processor of SASEBO‐W standard side‐channel analysis board. The authors used least squares support vector machine (LS‐SVM) based binary classifiers to analyse the collected power traces. The authors also describe the potential threat posed by cache timing attacks on Joye's ladder in presence of a concurrently running spy process and outline a probable countermeasure to the posed attacks.