Ultra‐step‐up dc–dc converter with low‐voltage stress on devices. Issue 3 (28th January 2019)

• Record Type: Journal Article
• Authors: Jalilzadeh, Tohid; Rostami, Naghi; Babaei, Ebrahim; Maalandish, Mohammad
• Is Part Of: IET power electronics. Volume 12:Issue 3(2019)
• Page Start: 345
• Page End: 357
• Publication Date: 2019-01-28
• Subjects: voltage multipliers -- DC‐DC power convertors -- field effect transistor switches -- charge pump circuits; circuit performance -- current stresses -- voltage analysis -- conduction losses -- turn‐on losses -- small duty cycle -- charge pump capacitor -- novel ultra‐step‐up DC–DC converter -- voltage gain -- reduced nominal voltage -- MOSFET switch -- high voltage gains -- input source -- switch off‐time -- switch on‐time -- inductors -- voltage multiplier cell -- self‐lift circuit -- conventional boost converter -- power devices -- low normalised voltage stress; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2018.5356
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : This study suggests a novel ultra‐step‐up dc–dc converter with low normalised voltage stress across the power devices. The proposed converter incorporates the conventional boost converter with a self‐lift circuit and charge pump concept and utilises a voltage multiplier cell at the output side. In the input side, two inductors are magnetised during the switch on‐time. During the switch off‐time, the stored energy in these inductors, charge pump capacitor and input source, is delivered to the load. Accordingly, the proposed converter is capable of providing high voltage gains with a small duty cycle. Besides, the voltage stress across the power devices is low. Therefore, the MOSFET switch with low R DS‐on and devices with reduced nominal voltage can be used which in turn reduces the conduction and turn‐on losses. The analysis of the voltage and current stresses is accomplished. The circuit performance is compared with other solutions in the literature in terms of voltage gain and normalised voltage stress of the semiconductors. Eventually, to validate the theoretical analysis, the experimental results are given.