Analysis and implementation of a generalised switched‐capacitor multi‐level inverter having the lower total standing voltage. Issue 17 (22nd January 2021)

• Record Type: Journal Article
• Authors: Majumdar, Saikat; Mahato, Bidyut; Jana, Kartick Chandra
• Is Part Of: IET power electronics. Volume 13:Issue 17(2020)
• Page Start: 4031
• Page End: 4042
• Publication Date: 2021-01-22
• Subjects: switched capacitor networks -- PWM invertors -- switching convertors -- capacitors; single isolated voltage source -- capacitors -- voltage levels -- total inverter DC link voltages -- hybrid generalised SC‐MLI -- constant voltage -- voltage gain -- minimum conducting paths -- conducting switches -- 17‐level inverters -- switched‐capacitor multilevel inverter -- total standing voltage; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2020.0458
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : Most of the switched capacitor multi‐level inverters (SC‐MLIs) are designed with a single isolated voltage source and capacitors where voltage levels are obtained by the addition of these sources only. The common problems arise in SC‐MLIs are an unequal number of conducting paths, higher voltage drop across capacitors, sum of total inverter DC link voltages across the highest voltage rated switches and higher total standing voltage (TSV). The motivation of this work is to design a hybrid generalized SC‐MLI with reduced components aiming to maintain a constant voltage across the capacitors, to achieve higher voltage gain with minimum components used, minimum conducting paths, lower TSV, cost‐effective and an efficient inverter. A generalised SC‐MLI structure is also proposed, which can multiply the voltage across the capacitors in a binary asymmetrical manner. The design parameters of the proposed hybrid SC‐MLI topology are compared with the recently developed SC‐MLIs in terms of the number of switches, capacitors, TSV, conducting switches and industrial components cost to prove its superiority and effectiveness of the proposed inverter. The experimental prototype of a specimen 9‐level and 17‐level inverters are implemented using DS1103 and the corresponding results are presented.