Analysis of dc‐link capacitor current in three‐level neutral point clamped and cascaded H‐bridge inverters. Issue 7 (1st August 2013)

• Record Type: Journal Article
• Authors: Orfanoudakis, Georgios I.; Yuratich, Michael A.; Sharkh, Suleiman M.
• Is Part Of: IET power electronics. Volume 6:Issue 7(2013)
• Page Start: 1376
• Page End: 1389
• Publication Date: 2013-08-01
• Subjects: invertors; dc‐link capacitor current -- three‐level neutral point clamped inverters -- cascaded H‐bridge inverters -- dc‐link capacitor sizing -- root‐mean‐square value -- harmonic spectrum -- two‐level inverters -- capacitor rms current -- voltage ripple -- MATLAB code -- modulation strategies -- higher‐level inverters -- capacitor sizing parameters -- three‐level topologies -- MATLAB‐Simulink; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2012.0422
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : Dc‐link capacitor sizing is a critical aspect of inverter design. This study investigates capacitor sizing for three‐level neutral‐point‐clamped and cascaded H‐bridge inverters, based on an analysis of dc‐link capacitor current. Methods used to derive expressions for the root‐mean‐square (rms) value and harmonic spectrum of the capacitor current in two‐level inverters, are extended to the three‐level inverters. A new numerical approach is also proposed for calculating the capacitor rms current and voltage ripple. MATLAB code is given for the proposed approach, which can be easily adapted to different modulation strategies and applied to higher‐level inverters. Capacitor sizing parameters derived according to this approach are presented for a number of common modulation strategies and are used to compare the requirements of the examined three‐level topologies. Results are validated by simulations using MATLAB‐Simulink.