Effect of adding DC‐offset estimation integrators in there‐phase enhanced phase‐locked loop on dynamic performance and alternative scheme. Issue 3 (1st March 2015)

• Record Type: Journal Article
• Authors: Wu, Fengjiang; Zhang, Lujie; Duan, Jiandong
• Is Part Of: IET power electronics. Volume 8:Issue 3(2015)
• Page Start: 391
• Page End: 400
• Publication Date: 2015-03-01
• Subjects: integrating circuits -- phase locked loops -- amplitude estimation -- frequency estimation -- power harmonic filters -- discrete Fourier transforms; DC‐offset estimation integrator -- there‐phase enhanced phase‐locked loop -- amplitude estimation -- frequency estimation -- phase angle estimation -- periodic ripple -- DCEI -- disturbance elimination -- 3P‐EPLL transient performance -- hybrid filtering 3P‐EPLL -- delayed‐signal cancellation -- sliding Goertzel transform‐based filter -- harmonic effect elimination; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2014.0317
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : Three‐phase enhanced phase‐locked loop (3P‐EPLL) can estimate the amplitude, frequency and phase angle of the positive sequence of the three‐phase inputs without using a synchronous reference frame. However, the presence of DC offsets in the inputs of the conventional 3P‐EPLL introduces a periodic ripple in the estimated information. Thus, DC‐offset estimation integrators (DCEIs) to estimate and feedback the DC component as an error signal are introduced in 3P‐EPLL to eliminate the disturbance. This study presents a comprehensive study of the transient performance of 3P‐EPLL with DCEIs, proving that a worse and longer dynamic period is caused by the coupling of the frequency and amplitude loop resulted from DCEI. Further, a hybrid filtering 3P‐EPLL based on delayed‐signal cancellation to reject the DC component and sliding Goertzel transform‐based filter to eliminate the effect of harmonics and unbalanced inputs is proposed. Thus, a correct estimation is achieved even under unbalanced inputs with both DC and harmonic components. A set of detailed experiments of the former three enhanced phase‐locked loops (EPLLs) are presented to display the deficit of the conventional EPLLs and better performance of the proposed scheme.