Pulse delay control for capacitor voltage balancing in a three‐level boost neutral point clamped inverter. Issue 2 (1st February 2015)

• Record Type: Journal Article
• Authors: Krishna, Remya; Soman, Deepak E.; Kottayil, Sasi K.; Leijon, Mats
• Is Part Of: IET power electronics. Volume 8:Issue 2(2015)
• Page Start: 268
• Page End: 277
• Publication Date: 2015-02-01
• Subjects: invertors -- DC‐DC power convertors -- PI control -- control system synthesis -- field programmable gate arrays -- digital control -- virtual instrumentation -- voltage control -- delays; pulse delay control -- capacitor voltage balancing -- three level boost neutral point clamped inverter -- multioutput DC‐DC converters -- cross regulation effect -- grid integration -- single input dual output boost converter -- three‐level switching scheme -- inductor ripple current -- proportional‐integral controller -- DC link voltage regulation -- state‐space averaging technique -- inductor current ripple averaging technique -- controller design -- Matlab -- Simulink -- digital controller -- Vertex 5‐FPGA -- Labview‐Compact‐Rio module; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2014.0103
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : The cross regulation effect in multi‐output DC/DC converters offers a reliable support for the grid integration of multilevel inverters by balancing the capacitor voltages. The capacitor voltage balancing by single input dual output boost converter is often realised by conventional three‐level switching scheme. The three‐level operation benefits lower inductor ripple current, but it limits the maximum possible compensation voltages. In this study, the entire operating modes of the boost converter is presented and all the possible cases which contribute to the voltage balancing are employed for balancing the capacitor voltages in a three‐level neutral point clamped inverter. A proportional‐integral controller based duty ratio control and pulse delay control are used for DC link voltage regulation and capacitor voltage balancing. Since the classical state‐space averaging technique is not suitable for SIDO converters, inductor current ripple averaging technique is utilised for controller design. The circuit simulation is performed in Matlab/Simulink. The digital controller is realised using the Virtex‐5FPGA in Labview/CompactRIO module. Both simulation and experimental results are presented to validate the controller performance.