Fast minimum loss space vector pulse‐width modulation algorithm for multilevel inverters. Issue 6 (1st June 2014)

• Record Type: Journal Article
• Authors: Sozer, Yilmaz; Torrey, David A.; Saha, Aparna; Nguyen, Hung; Hawes, Nathaniel
• Is Part Of: IET power electronics. Volume 7:Issue 6(2014)
• Page Start: 1590
• Page End: 1602
• Publication Date: 2014-06-01
• Subjects: PWM invertors -- power grids; fast minimum loss space vector pulse‐width modulation algorithm -- multilevel inverters -- minimum loss space vector PWM algorithm -- three‐level inverters -- duty cycle limitation -- maximum DC bus utilisation -- minimum cycle time -- embedded controllers -- Matlab‐Simulink environment -- grid interactive inverter -- renewable energy application; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2013.0423
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : This study focuses on developing fast, easily implementable minimum loss space vector pulse‐width modulation (PWM) algorithms for three‐level inverters that can work through extended region of operation into over modulation. A unique way of duty cycle limitation for the maximum dc bus utilisation and the minimum loss PWM techniques is organised in the algorithm in a way to require minimum cycle time from embedded controllers. The developed control algorithm is tested in the Matlab/Simulink environment for the grid interactive inverter. The algorithm is experimentally evaluated on a system developed for a 15 kW grid interactive inverter for a renewable energy application. The simulation and experimental results show that proposed algorithm is very efficient and represents an easily implementable minimum loss space vector PWM algorithm for multilevel inverters.