Design of integer‐N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems. Issue 1 (1st January 2020)

• Record Type: Journal Article
• Authors: Berber, Zakia; Kameche, Samir; Benkhelifa, Elhadj
• Is Part Of: IET networks. Volume 9:Issue 1(2020)
• Page Start: 23
• Page End: 28
• Publication Date: 2020-01-01
• Subjects: phase noise -- circuit tuning -- passive filters -- frequency synthesizers -- phase locked loops -- jitter -- voltage‐controlled oscillators -- millimetre wave oscillators -- 5G mobile communication; PN -- time 0.39 ps -- time 0.40 ps -- bandwidth 10.0 MHz -- bandwidth 1.0 MHz -- frequency 81.0 GHz to 86.0 GHz -- frequency 71.0 GHz to 76.0 GHz -- ADIsimPLL tool -- 5G E‐band frequency -- integer‐N PLL frequency synthesiser design -- offset frequency -- phase noise -- phase margin -- external reference oscillator -- loop filter -- ADF4155‐PLL chip -- phase‐locked loop frequency synthesiser -- 5G communication systems -- high phase noise performance -- low reference spurs -- third‐order passive filter; Computer network architectures -- Periodicals; Computer network protocols -- Periodicals; Information networks -- Periodicals; Telecommunication systems -- Periodicals; 004.605
• DOI: 10.1049/iet-net.2018.5245
• Languages: English
• ISSNs: 2047-4954

Abstract

Abstract : A phase‐locked loop (PLL) frequency synthesiser is designed for 5G E‐band frequency. ADF4155‐PLL chip with an external (loop filter, prescaler, VCO and an external reference oscillator) is simulated using the ADIsimPLL tool. With a third‐order passive filter having 1 MHz loop bandwidth and 45° phase margin, simulation results show that the proposed synthesiser achieves a total phase noise (PN) of −81.50 and −115.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for (71–76 GHz) and −80.39 and −114.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for the highest (81–86 GHz) 5G frequency range even if −160 dBc/Hz VCO noise floor and −170dBc/Hz reference PN floor are integrated in the design. Also, the performance of the system in terms of RMS jitter and reference spurs are verified. The proposed synthesiser for 5G application presents very low reference spurs (−113, −112 dBc) at 50 MHz offset frequency and low RMS jitter (0.39, 0.40 ps) for 70 and 80 GHz frequency band, respectively.