65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing. Issue 3 (26th February 2020)

• Record Type: Journal Article
• Authors: Wen, Liang; Nan, Longmei; Zhang, Jing; Meng, Chunning; Lu, Yan; Qi, Shiqian; Lv, Jianping; Zhang, Yuejun
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 3(2020)
• Page Start: 303
• Page End: 310
• Publication Date: 2020-02-26
• Subjects: logic design -- logic circuits -- logic gates -- threshold logic -- trigger circuits -- leakage currents -- low-power electronics; sub-threshold standard cell library -- quasiSchmitt-trigger logic design scheme -- inverse narrow width effect aware sizing method -- logic cells -- conventional logic circuits -- sub-threshold region -- sub-threshold logic standard cell library -- quintessence -- Ion-to-Ioff ratio -- leakage current -- NOR3 logics -- NAND3 logics -- power-delay product -- process variation immunity -- leakage power reduction -- size 65.0 nm; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0028
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this study, the authors propose a sub‐threshold standard cell library in which the quintessence is a quasi‐Schmitt‐trigger logic design scheme and the inverse narrow width effect aware sizing method. The techniques can improve the I on ‐to‐ I off ratio of the logic cells effectively and provide a significant suppression in leakage current, enhancing the robustness of the circuits. Simulation results show that the NAND3 and NOR3 logics with the new techniques achieve 40–60% and 30–50% reductions in leakage power compared with conventional logic circuits, respectively, when the voltage is scaled down to sub‐threshold region. Again, they also exhibit considerable improvements in process variation immunity and power‐delay product.