3‐5 GHz multifinger CMOS LNA using a simultaneous noise and impedance matching technique by a significant reduction of broadband impedance variation of metal–oxide–semiconductor field effect transistor. Issue 7 (21st October 2020)

• Record Type: Journal Article
• Authors: Reza, Sakib; Roy, Apratim
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 7(2020)
• Page Start: 956
• Page End: 965
• Publication Date: 2020-10-21
• Subjects: impedance matching -- low noise amplifiers -- CMOS analogue integrated circuits -- wideband amplifiers -- integrated circuit layout -- MMIC amplifiers; average power gain -- CS‐input‐matched LNA -- simultaneous noise -- input matching technique -- broadband impedance variation -- metal–oxide–semiconductor field effect transistor -- ultrawideband low‐noise amplifier -- complementary metal–oxide–semiconductor process -- advanced design system platform -- multifinger layout technique -- shunt passive elements -- SNIM method -- noise figure -- amplifier port parameters -- contour plots -- SNIM technique -- post‐layout electromagnetic simulated NF -- multifinger CMOS LNA -- two‐dimensional contour plot‐based process variation tolerant bias voltage setup protocol -- common gate‐input‐matched LNA -- common source‐input‐matched LNA -- size 0.18 mum -- noise figure 3.08 dB to 4.1 dB -- power 20.19 mW -- noise figure 2.772 dB to 3.04 dB -- power 20.73 mW -- frequency 3.0 GHz to 5.0 GHz -- gain 25.52 dB -- gain 17.98 dB; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0519
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low‐noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)‐ and common source (CS)‐input‐matched LNAs are designed where the variation of input impedance over the whole operating band is significantly reduced by applying the multifinger layout technique and employing shunt passive elements for the input device without degenerating the structure, respectively. As part of the proposed SNIM method, a two‐dimensional contour plot‐based process variation tolerant bias voltage set up protocol is developed which can optimise forward gain ( S 21 ), noise figure (NF) and stability factor simultaneously. The regulation of amplifier port parameters with bias settling contour plots and finger parameters results in the proposed SNIM technique. For the CG‐input‐matched LNA, the post‐layout electromagnetic simulated NF is between 3.08 and 4.1 dB, the average power gain of 25.52 dB with a power consumption of 20.19 mW and the CS‐input‐matched LNA achieves an NF in between 2.772 and 3.04 dB, the average power gain of 17.98 dB while the dissipated power is 20.73 mW.