Six‐track multi‐finger standard cell library design for near‐threshold voltage operation in 130 nm complementary metal oxide semiconductor technology. Issue 5 (18th July 2019)

• Record Type: Journal Article
• Authors: Lim, Yang Wei; Kamsani, Noor Ain; Sidek, Roslina Mohd; Hashim, Shaiful Jahari; Rokhani, Fakhrul Zaman
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 5(2019)
• Page Start: 710
• Page End: 716
• Publication Date: 2019-07-18
• Subjects: CMOS integrated circuits -- integrated circuit layout -- circuit optimisation; near-threshold voltage operation -- multifinger layout structure -- digital circuit design -- near-threshold operation -- parasitic effects -- inverse narrow width effect -- based width unit -- design area -- eight-track multiplier layout libraries -- block design level -- multiplier structure library -- complementary metal oxide semiconductor technology -- six-track multifinger standard cell library design -- energy efficiency -- performance enhancement -- automatic place-and-route -- minimum critical path delay -- size 130.0 nm; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5542
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this study, a six‐track standard cell library with a multi‐finger layout structure is proposed to improve the delay, energy, and area of the digital circuit design for near‐threshold operation. The proposed library is optimised by using the parasitic effects of the technology and optimising the layout. To enhance the performance and energy efficiency, inverse narrow width effect has been considered in the design, whereby the minimum width of the process was used as the based width unit. To minimise the design area, the standard cell was designed in the lowest possible height with a multi‐finger layout structure. The proposed library with a few basic cells was developed and characterised in 130 nm technology, which is available for synthesis and automatic place‐and‐route (P&R). The proposed library was analysed and compared with two eight‐track multiplier layout libraries in the cell and block design level. Based on the place‐and‐route results of ISCAS'85 benchmark circuits, the proposed six‐track library could achieve up to 27% of delay improvement, 29% energy reduction and 44% area reduction as compared to the multiplier structure library at the minimum critical path delay.