CMOS injection‐locked frequency divider with division factor of three. Issue 1 (1st January 2016)

• Record Type: Journal Article
• Authors: Dehghani, Rasoul
• Is Part Of: IET circuits, devices & systems. Volume 10:Issue 1(2016)
• Page Start: 68
• Page End: 77
• Publication Date: 2016-01-01
• Subjects: CMOS integrated circuits -- frequency dividers -- injection locked oscillators -- integrated circuit layout -- wiring -- electric resistance -- capacitance -- inductance; three division factor -- complementary metal oxide semiconductor -- divide-by-3 injection locked frequency divider -- two-stage differential ring oscillator -- quadrature signal -- injection signal -- divider locking range -- CMOS technology -- power dissipation -- layout wiring parasitic element -- resistance -- capacitance -- inductance -- size 0.18 mum -- voltage 1.8 V -- frequency 1 GHz to 4.2 GHz -- power 505 muW; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2014.0363
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : A divide‐by‐3 injection locked frequency divider is presented. The divider works based on a two‐stage differential ring oscillator in which two quadrature signals are used as injection signals. The analytical relationship for the divider locking range is derived and the main factors impacting on this parameter are discussed. The circuit has been designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V. Post layout simulation on the divider including all layout wiring parasitic elements such as resistance, capacitance and inductance shows that the typical locking range of the divider is over 3 GHz from 1 to 4.2 GHz for −0.5 dBm injection signal level while its total power dissipation for 4.2 GHz input injection signal is 505 μW at the supply of 1.8 V.