Reduced switching mode for SAR ADCs: analysis and design of SAR A‐to‐D algorithm with periodic standby mode circuit components. Issue 5 (20th July 2020)

• Record Type: Journal Article
• Authors: Joshi, Ashish; Shrimali, Hitesh; Sharma, Satinder K.
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 5(2020)
• Page Start: 686
• Page End: 694
• Publication Date: 2020-07-20
• Subjects: analogue-digital conversion -- CMOS digital integrated circuits -- low-power electronics -- integrated circuit design; switching mode -- periodic standby mode circuit components -- RSw mode design -- input frequency -- dispensable switching activity -- periodic temporal reference -- sampling frequency -- design criterion -- digital circuitry -- core ADC -- analogue-to-digital converter specifications -- reduced switching activity mode successive approximation register analogue-to-digital algorithm -- SAR A-to-D algorithm -- signal variation -- numerical mathematics -- signal-to-noise and distortion ratio -- behavioural simulations -- Matlab-Simulink -- standard CMOS technology -- fully differential ADC -- size 180.0 nm -- word length 9.7 bit -- voltage 1.8 V -- word length 10 bit; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0224
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This study presents the analysis and design of reduced switching (RSw) activity mode successive approximation register (SAR) analogue‐to‐digital (A‐to‐D) algorithm. For given analogue‐to‐digital converter (ADC) specifications, RSw mode design is based on the observation that the signal variation in two successive samples becomes linear over a certain range of input frequencies. Hence, dispensable switching activity between the two samples can be eliminated by enabling periodic temporal reference to the converter. No prediction or logic circuitry is required to extract information from previous bits. However, there exists a trade‐off between the input frequency and the sampling frequency. A design criterion is derived using numerical mathematics to skip evaluation of the optimum number of bits while maintaining the desired signal‐to‐noise and distortion ratio. The design criterion is validated through behavioural simulations using MATLAB/Simulink ® . Furthermore, a fully differential 10‐bit, 104 kS/s ADC is designed in a standard 180 nm CMOS technology to demonstrate circuit implementation of the RSw mode. In the RSw mode, power dissipation in the comparator and relevant digital circuitry decreases by 20%. The ADC achieves low‐frequency effective number of bits of 9.7 bits and spurious free dynamic range of 68.3 dB. With 1.8 V supply voltage, average power dissipation in the core ADC is 2.54 μW; resulting in figure‐of‐merit of 29.3 fJ/conv‐step.