Variation resilient reliable design of trigger pulse generator. Issue 6 (7th September 2020)
- Record Type:
- Journal Article
- Title:
- Variation resilient reliable design of trigger pulse generator. Issue 6 (7th September 2020)
- Main Title:
- Variation resilient reliable design of trigger pulse generator
- Authors:
- Kumar, Amresh
Dwivedi, Amit Krishna
Islam, Aminul - Abstract:
- Abstract : This study presents a robust design of a trigger pulse generator that produces trigger pulses of variable widths/durations that are tuned using an external control as per the requirements. The proposed design comprises two elementary modules: a delay element and an XOR circuit. The proposed circuit is implemented using a 16 nm CMOS technology node and simulation results have been verified using the SPICE simulator. Various performance parameters such as power consumption, power delay‐product, energy‐delay product and impact of key circuit parameters [supply voltage ( V DD ), channel length ( L g), gate width ( W g), channel doping concentration ( N A ), oxide thickness ( T OX ), threshold voltage ( V T ) and carrier mobility ( µ o )] on the duration of trigger pulses have been studied in‐depth and performance parameters are compared with circuits already available in the literature. The proposed circuit produces trigger pulses of a minimum width of 191.3 ps at a nominal supply of 1.0 V with an average power consumption of 160 nW. The width of the trigger pulses can be varied from 191.3 to 457.2 ps using an external control from 1.0 to 0.7 V, respectively, at 16 nm technology node.
- Is Part Of:
- IET circuits, devices & systems. Volume 14:Issue 6(2020)
- Journal:
- IET circuits, devices & systems
- Issue:
- Volume 14:Issue 6(2020)
- Issue Display:
- Volume 14, Issue 6 (2020)
- Year:
- 2020
- Volume:
- 14
- Issue:
- 6
- Issue Sort Value:
- 2020-0014-0006-0000
- Page Start:
- 860
- Page End:
- 868
- Publication Date:
- 2020-09-07
- Subjects:
- CMOS logic circuits -- pulse generators -- trigger circuits -- integrated circuit reliability -- logic design -- delay circuits
variation resilient reliable design -- trigger pulse generator -- XOR circuit -- power delay‐product -- energy‐delay product -- delay element -- CMOS technology node -- SPICE simulator -- power consumption -- supply voltage -- channel length -- gate width -- channel doping concentration -- oxide thickness -- threshold voltage -- carrier mobility -- size 16.0 nm -- power 160.0 nW -- time 191.3 ps to 457.2 ps -- voltage 0.7 V to 1.0 V
Electronic circuits -- Periodicals
Electronic systems -- Periodicals
621.381505 - Journal URLs:
- https://ietresearch.onlinelibrary.wiley.com/journal/17518598 ↗
http://ieeexplore.ieee.org/servlet/opac?punumber=4123966 ↗
http://www.theiet.org/ ↗
http://digital-library.theiet.org/content/journals/iet-cds ↗
http://www.ietdl.org/IET-CDS ↗ - DOI:
- 10.1049/iet-cds.2019.0362 ↗
- Languages:
- English
- ISSNs:
- 1751-858X
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 4363.252190
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 16490.xml