New energy‐efficient hybrid wide‐operand adder architecture. Issue 8 (12th November 2019)

• Record Type: Journal Article
• Authors: Jafarzadehpour, Fereshteh; Molahosseini, Amir Sabbagh; Emrani Zarandi, Azadeh Alsadat; Sousa, Leonel
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 8(2019)
• Page Start: 1221
• Page End: 1231
• Publication Date: 2019-11-12
• Subjects: low-power electronics -- energy conservation -- carry logic -- adders -- VLSI -- power aware computing; low-power adders -- adder architectures -- parallel-prefix adders -- high-power consumption -- hybrid design -- power-consumption -- least-significant positions -- summation least-significant bits -- most-significant positions -- energy-efficient hybrid wide-operand adder architecture; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0084
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : The consumer electronics markets have increased the demand for high‐speed and low‐power adders with large operands to be integrated in modern portable systems. Traditional fast adder architectures, such as parallel‐prefix adders, exhibit high‐power consumption for large operands. The hybrid design is one of the most promising techniques to achieve a trade‐off between the delay and power‐consumption for the addition of large operands. This study presents a new hybrid adder architecture, specifically designed for large operands, based on the premise that in large parallel‐prefix adders the least‐significant carries are produced much sooner than the most‐significant ones. Therefore, the authors avoid the incorporation of fast architectures related with the application of carries to the final summation least‐significant bits, with no impact on the critical path. This leads to a reduction in the area of the summation blocks in the least‐significant positions without compromising the speed. Moreover, the complement of the carries is generated and propagated inside the carry network of the proposed adder in order to decrease the delay. VLSI implementation results on the 65‐nm‐TSMC technology show that the proposed adder achieves >25% of energy savings, and a reduction of over 30% of the area‐delay‐product in comparison with state‐of‐the‐art wide‐operand adders.