Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array. Issue 3 (1st May 2016)
- Record Type:
- Journal Article
- Title:
- Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array. Issue 3 (1st May 2016)
- Main Title:
- Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array
- Authors:
- Sworna, Zarrin Tasnim
UlHaque, Mubin
Tara, Nazma
Hasan Babu, Hafiz Md.
Biswas, Ashis Kumar - Abstract:
- Abstract : The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT‐based BCD adder which is constructed basically in three steps: First, a new technique is introduced for the BCD addition to obtain the correct BCD digit. Second, a new controller circuit of LUT is presented which is designed to select and send Read/Write voltage to memory cell for performing Read or Write operation. Finally, a compact BCD adder is designed using the proposed LUT. Their proposed 2‐input LUT outperforms the existing best one providing 65.8% improvement in terms of area, 44.1% for Read operation and 43.5% for Write operation in power consumption. The proposed BCD adder using FPGA gains a radical achievement compared with the existing best‐known LUT‐based BCD adder providing prominent better performance of 65.6% in area and 48.3% less power consumption.
- Is Part Of:
- IET circuits, devices & systems. Volume 10:Issue 3(2016)
- Journal:
- IET circuits, devices & systems
- Issue:
- Volume 10:Issue 3(2016)
- Issue Display:
- Volume 10, Issue 3 (2016)
- Year:
- 2016
- Volume:
- 10
- Issue:
- 3
- Issue Sort Value:
- 2016-0010-0003-0000
- Page Start:
- 163
- Page End:
- 172
- Publication Date:
- 2016-05-01
- Subjects:
- field programmable gate arrays -- binary codes -- adders -- low-power electronics -- table lookup
field programmable gate array -- FPGA -- low-power area efficient binary coded decimal adder -- look up table -- BCD addition -- BCD digit -- controller circuit -- read-write voltage -- memory cell -- read operation -- write operation -- compact BCD adder -- 2-input LUT -- power consumption
Electronic circuits -- Periodicals
Electronic systems -- Periodicals
621.381505 - Journal URLs:
- https://ietresearch.onlinelibrary.wiley.com/journal/17518598 ↗
http://ieeexplore.ieee.org/servlet/opac?punumber=4123966 ↗
http://www.theiet.org/ ↗
http://digital-library.theiet.org/content/journals/iet-cds ↗
http://www.ietdl.org/IET-CDS ↗ - DOI:
- 10.1049/iet-cds.2015.0213 ↗
- Languages:
- English
- ISSNs:
- 1751-858X
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 4363.252190
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 16489.xml