Design of energy‐efficient ternary circuits using differential cascode voltage switch strategies in carbon nanotube field effect transistor technology. Issue 7 (27th October 2020)

• Record Type: Journal Article
• Authors: Sharma, Trapti; Kumre, Laxmi
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 7(2020)
• Page Start: 1077
• Page End: 1085
• Publication Date: 2020-10-27
• Subjects: ternary logic -- low‐power electronics -- logic design -- CMOS logic circuits -- SPICE -- logic gates -- carbon nanotube field effect transistors -- voltage dividers; static diode voltage divider topology -- ternary designs -- DCVS logic style -- energy consumption -- ternary DCVS circuits -- HSPICE synopsis simulator -- logical operations -- power reduction -- energy reduction -- shifting operators -- process variation effects -- energy‐efficient ternary circuits -- differential cascode voltage switch strategies -- carbon nanotube field effect transistor technology -- static technique -- layout density -- logic flexibility -- power consumption -- DCVS‐based ternary logic gates -- unary operators -- DCVS designs -- size 32.0 nm -- C; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0375
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Differential cascode voltage switch (DCVS) is a static technique which offers the advantages of layout density, logic flexibility together with improved delay and power consumption. In this study, DCVS‐based ternary logic gates and unary operators are reported using static diode voltage divider topology. The main focus of the proposed ternary designs using DCVS logic style is to provide minimum energy consumption with less area overhead. In the presented method, a new power efficient and compact solution is being provided to improve the driving capability of the ternary DCVS circuits. All the simulations are performed on HSPICE synopsis simulator using 32 nm technology under different operational conditions. For the inversion and logical operations, the proposed method has a maximum power reduction of 45% and an energy reduction of 30% as compared to earlier reported DCVS designs. In the case of shifting operators, the maximum power reduction of 38.93% and an energy reduction of 39% are achieved. The design performance is robust when subjected to various process variation effects and have sufficient noise margins.