Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms. Issue 8 (12th November 2019)

• Record Type: Journal Article
• Authors: Panda, Madhusmita; Kumar Patnaik, Santosh; Kumar Mal, Ashis; Ghosh, Sumalya
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 8(2019)
• Page Start: 1187
• Page End: 1195
• Publication Date: 2019-11-12
• Subjects: evolutionary computation -- particle swarm optimisation -- analogue-digital conversion -- voltage-controlled oscillators -- phase noise -- low-power electronics -- microwave oscillators -- decision diagrams -- integrated circuit noise; word length 4.0 bit -- frequency 3.49 GHz -- frequency 1.0 MHz -- frequency 10.0 MHz -- power consumption -- nfeasibility-driven evolutionary algorithm -- noise analysis -- noise modelling -- differential voltage controlled oscillator -- layered determinant expansion -- VCO-based ADC -- optimum design parameters -- low-phase noise -- multiobjective particle swarm optimisation -- DDD technique -- symbolic method -- multiobjective algorithms -- differential VCO -- SPICE -- IDEA optimisation approach; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5617
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this work, a DVCO has been designed for a 4‐bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi‐objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.