3D‐IC partitioning method based on genetic algorithm. Issue 7 (27th October 2020)

• Record Type: Journal Article
• Authors: Meitei, Naorem Yaipharenba; Baishnab, Krishna Lal; Trivedi, Gaurav
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 7(2020)
• Page Start: 1104
• Page End: 1109
• Publication Date: 2020-10-27
• Subjects: search problems -- three‐dimensional integrated circuits -- integrated circuit layout -- simulated annealing -- genetic algorithms -- integrated circuit design; thermal‐aware 3D partitioning technique -- genetic algorithm -- tier partitioning algorithm -- three‐dimensional integrated circuits -- design parameters -- 3D IC partitioning method -- average layer power density -- through‐silicon vias -- fixed‐outline constraint -- mutation operation -- complement mutation -- simulated annealing; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2020.0128
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this study, a new tier partitioning algorithm for three‐dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through‐silicon vias (TSVs) subject to fixed‐outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover and complement mutation, is employed for optimisation of design variables. Experimental results exhibit that the authors proposed method reduces the average number of TSVs by 45.75 and 44.68%, as compared to taboo search and simulated annealing‐based 3D partitioning methods. It also reduces the average number of TSVs, maximum power density among the layers and average layer area by 28.34, 40.29, and 27.85%, respectively, as compared to thermal‐aware 3D partitioning technique. The results of their proposed algorithm demonstrate the efficiency and effectiveness in tier partitioning for 3D ICs over existing methods.