Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC. Issue 5 (15th July 2020)

• Record Type: Journal Article
• Authors: Hussain, Sarfraz; Kumar, Rajesh; Trivedi, Gaurav
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 5(2020)
• Page Start: 629
• Page End: 639
• Publication Date: 2020-07-15
• Subjects: encoding -- analogue-digital conversion -- error correction -- binary codes -- tree codes -- logic design; higher order bubble correction -- BEC -- 4-bit encoder -- bubble error corrector -- 1-GSPS flash type ADC -- bubble error correction -- flash analogue-to-digital converter -- binary encoder -- Fat-Tree encoder -- NAND gate -- OR gate -- power 18.3563 pW -- voltage 1.8 V -- energy 3.335 fJ -- power 87.071 muW; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0499
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : The design of a 4‐bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue‐to‐digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one‐hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat‐Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power‐delay product of 3.335 fJ, energy‐delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .