High‐speed, low power, and dead zone improved phase frequency detector. Issue 7 (21st October 2019)

• Record Type: Journal Article
• Authors: Fathi, Amir; Mousazadeh, Morteza; Khoei, Abdollah
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 7(2019)
• Page Start: 1056
• Page End: 1062
• Publication Date: 2019-10-21
• Subjects: low-power electronics -- integrated circuit design -- phase detectors -- flip-flops -- integrated circuit layout -- CMOS logic circuits; dead zone improved phase frequency detector -- PFD -- architectural simplicity -- power consumption -- power dissipation -- pass transistor logic -- post-layout simulation -- latch configuration -- static transistor logic -- HSPICE -- TSMC CMOS technology -- high-speed phase frequency detector -- low power phase frequency detector -- frequency 1.0 GHz -- power 277.0 muW -- voltage 1.8 V -- size 0.18 mum; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0135
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Design of a novel phase frequency detector (PFD) has been presented here. The innovative advantage of the proposed structure is its improved dead zone performance due to the architectural simplicity which is a combination of static and pass transistor logic (PTL)‐based latch configuration. Due to low latency from inputs to the outputs, the operating frequency of the proposed circuit is high while its power consumption is very low. Analytics along with simulations have confirmed the correct behaviour of the designed circuit. For better evaluation of designed architecture advantages, two of the last reported works have been redesigned and simulated along with the proposed PFD. The post‐layout simulation results using HSPICE with TSMC 0.18 µm CMOS technology and 1.8 V power supply demonstrate the operating frequency of 1 GHz for the designed circuitry while the power dissipation is 277 µW and the measured dead zone is π / 11 as an enormous enhancement over previous works.