Spur reduction architecture for multiphase fractional PLLs. Issue 8 (12th November 2019)

• Record Type: Journal Article
• Authors: Biswas, Debdut; Bhattacharyya, Tarun Kanti
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 8(2019)
• Page Start: 1169
• Page End: 1180
• Publication Date: 2019-11-12
• Subjects: phase locked loops -- phase detectors -- charge pump circuits -- UHF filters -- UHF oscillators -- voltage control; spur reduction architecture -- multiphase fractional phase-locked loop -- phase errors -- adjacent phases -- phase correction circuit -- oscillator phase generator -- loop filter control voltage -- residual spurs -- multiphase fractional PLL -- fractional spur -- voltage filtering -- phase-frequency detector -- charge pump -- PFD nonidealities -- moving average filter -- frequency 400.0 MHz -- size 180.0 nm; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0041
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this study, a multiphase fractional phase‐locked loop (PLL) is presented with methods to reduce spurs. General causes of spurs are non‐idealities of the phase‐frequency detector (PFD) and charge pump (CP) and phase errors between the adjacent phases from the oscillator. In the architecture, the non‐idealities of the PFD and CP are compensated and a phase correction circuit is added after the oscillator phase generator to reduce the phase errors, and hence minimise the spurs. Spurs may still be persistent after these modifications due to process variations and device mismatch. The effect is visible in the perturbations of the loop filter control voltage. The residual spurs are minimised by further filtering the control voltage using a moving average filter and then applying it to the oscillator. The PLL is designed in 180 nm technology and outputs a 400 MHz carrier. The highest fractional spur is decreased from −36 to −66 dBc through phase correction and control voltage filtering.