Calibration method to reduce the error in logarithmic conversion with its circuit implementation. Issue 4 (7th March 2018)

• Record Type: Journal Article
• Authors: Zhao, Zhou; Srivastava, Ashok; Peng, Lu; Mohanty, Saraju P.
• Is Part Of: IET circuits, devices & systems. Volume 12:Issue 4(2018)
• Page Start: 301
• Page End: 308
• Publication Date: 2018-03-07
• Subjects: calibration -- binary codes -- clocks -- CMOS logic circuits; calibration method -- circuit implementation -- Mitchell's logarithmic conversion -- fast calibration method -- fixed binary code -- conversion error -- highly paralleled circuit -- differential cascade voltage switch logic -- high-speed logic -- adiabatic logic -- power dissipation -- low-cost adiabatic clock generator -- passive component -- four-phase sine clock -- logarithmic converter -- CMOS -- word length 8 bit -- size 180 nm -- power 1.12 mW -- power 3.709 mW -- time 1.82 ns; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2017.0315
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high‐speed logic and adiabatic logic and trade‐off between power dissipation and operation speed. In addition, a low‐cost adiabatic clock generator without any passive component is presented to support a four‐phase sine clock for the adiabatic logic operation. An 8‐bit logarithmic converter is designed in TSMC 180 nm CMOS. Post‐simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.