Resistance‐to‐digital converter designed for high power‐line interference rejection capability. Issue 5 (21st February 2017)

• Record Type: Journal Article
• Authors: Gupta, Rohit; George, Boby
• Is Part Of: IET circuits, devices & systems. Volume 11:Issue 5(2017)
• Page Start: 446
• Page End: 451
• Publication Date: 2017-02-21
• Subjects: analogue-digital conversion -- electromagnetic interference -- power cables -- error analysis; LTSPICE -- error analysis -- analogue-to-digital converter -- high power-line interference rejection capability -- RDC -- resistance-to-digital converter design; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2016.0236
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : A novel resistance‐to‐digital converter (RDC), based on the integrating type analogue‐to‐digital converter principle, is presented in this study. The conversion time of the proposed scheme is not a function of the current value of the parameter being measured. Thus, by suitably setting this parameter, the converter can be made to reject the effects of interference at a particular frequency, such as, that due to power‐line at 50/60 Hz. Error analysis was conducted to ascertain the effects of non‐idealities of various components of the circuit, on its output. Simulation studies were carried out in LTSPICE to verify the linearity and the interference rejection capability of the converter. Further, a prototype RDC was developed in the laboratory and tested to confirm the results of the simulation.