0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application. Issue 7 (17th October 2019)

• Record Type: Journal Article
• Authors: Zhang, Zhao; Yang, Jincheng; Liu, Liyuan; Qi, Nan; Feng, Peng; Liu, Jian; Wu, Nanjian
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 7(2019)
• Page Start: 1071
• Page End: 1077
• Publication Date: 2019-10-17
• Subjects: CMOS integrated circuits -- low-power electronics -- frequency synthesizers -- phase noise -- software radio -- multiplexing equipment; software-defined radio application -- lower band frequency output -- low-power applications -- low power mode -- low band frequency signal -- frequency selection multiplexer -- power consumption -- high carrier frequency -- wideband ΔΣ fractional-N frequency synthesiser -- WBFS -- FSMUX -- adjustable replica bias circuit -- size 65.0 nm -- frequency 1.0 MHz -- power 21.0 mW -- power 10.2 mW -- frequency 0.1 GHz to 5.0 GHz -- voltage 1.2 V; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5271
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This article proposes a wideband ΔΣ fractional‐N frequency synthesiser (WBFS) for software‐defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low‐power mode for the low‐power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide‐by‐two divider chain to optimise the power consumption at different frequencies while keep the output swing constant at different bias current to achieve robust operation. The FSMUX is implemented in differential structure instead of the widely used quadrature structure to reduce power and area especially at high carrier frequency. Implemented in 65 nm CMOS process with a 1.2‐V supply, the WBFS generates frequency from 0.1 to 5 GHz. The maximum power at regular and low‐power mode is 21 and 10.2 mW, respectively. The phase noise is −120.3 dBc/Hz at 1 MHz offset (2.75375 GHz) at regular mode and −122.8 dBc/Hz at 1 MHz offset (1.3525 GHz) at low‐power mode. Thanks to the differential FSMUX with the proposed AR bias circuit and the low‐power mode, the WBFS power is significantly reduced, compared with that of the prior WBFS with comparable frequency range.