Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self‐Tracking Comparator Thresholds. Issue 3 (1st July 2015)

• Record Type: Journal Article
• Authors: Wang, Ke; Fan, Chaojie; Pan, Wenjie; Zhou, Jianjun
• Is Part Of: Chinese journal of electronics. Volume 24:Issue 3(2015)
• Page Start: 474
• Page End: 479
• Publication Date: 2015-07-01
• Subjects: amplifiers -- analogue‐digital conversion -- calibration -- comparators (circuits); nonlinearity calibration -- splitting capacitors -- self‐tracking comparator thresholds -- digital background calibration technique -- pipelined analog‐to‐digital converters -- ADC -- signal‐to‐noise‐and‐distortion ratio -- SNDR -- spurious‐free dynamic range; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2015.07.006
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : A digital background calibration technique which mainly corrects nonlinear errors of residue amplifiers in pipelined analog‐to‐digital converters (ADCs) is presented. The proposed technique extracts the nonlinear errors by splitting sampling capacitors and inserting two extra comparators, and is highly effective as long as the input signal is busy. The method of self‐tracking comparator thresholds is proposed to reduce the time of convergence with low complexity for any bit cases in a pipelined ADC. Both measurement and correction are processed in digital domain. After calibration, the behavioral simulation shows that the Signal‐to‐noise‐and‐distortion ratio (SNDR) is raised from 55.4dB to 90.2dB and the Spurious‐free dynamic range (SFDR) is improved from 61.6dB to 102dBin a 16‐bit prototype pipelined ADC with 0.5% capacitor mismatches and 4.5% gain compression of the residue amplifier.