An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96. Issue 5 (1st September 2016)
- Record Type:
- Journal Article
- Title:
- An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96. Issue 5 (1st September 2016)
- Main Title:
- An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96
- Authors:
- He, Zhiyong
Zhao, Qiang
Xu, Hushan
Cui, Wenjuan
Luo, Yuxi - Abstract:
- Abstract : We propose a class of Rate‐compatible (RC) Low‐density parity‐check (LDPC) codes with a very wide range of code rates. To widen the range of rates, we have developed an optimal transmission scheme to push the upper bound of code rates to 0.96. Characterized by a parity check matrix in a dual‐diagonal form, the proposed RC LDPC code can be encoded in linear time. Constructed from shifted identity sub‐matrices, the proposed codes are particularly well‐suited for the high‐speed implementation of parallel encoders. Furthermore, the encoder can be implemented efficiently with several left circular shifters and XOR gates. To maximize the encoding speed, we have proposed a q ‐parallel encoder architecture, where q is the size of each sub‐matrix. The implementation results into Field programmable gate array (FPGA) devices indicate that a 72‐parallel encoder for the proposed RC LDPC code with a code rate from 0.5 to 0.96 is capable of reaching a speed of 42 Gigabits per second (Gbps) using a clock frequency of 300MHz.
- Is Part Of:
- Chinese journal of electronics. Volume 25:Issue 5(2016)
- Journal:
- Chinese journal of electronics
- Issue:
- Volume 25:Issue 5(2016)
- Issue Display:
- Volume 25, Issue 5 (2016)
- Year:
- 2016
- Volume:
- 25
- Issue:
- 5
- Issue Sort Value:
- 2016-0025-0005-0000
- Page Start:
- 921
- Page End:
- 927
- Publication Date:
- 2016-09-01
- Subjects:
- Low‐density parity‐check codes (LDPC) -- High‐speed encoder -- Field programmable gate array (FPGA) implementation
field programmable gate arrays -- matrix algebra -- parity check codes
RC LDPC codes -- rate compatible RC -- low density parity check -- optimal transmission scheme -- parity check matrix -- dual diagonal form -- shifted identity submatrices -- XOR gates -- left circular shifters -- encoding speed -- q‐parallel encoder architecture -- field programmable gate array -- FPGA
Electronics -- Periodicals
Electronics -- China -- Periodicals
Electronics
China
Periodicals
621.38105 - Journal URLs:
- https://ietresearch.onlinelibrary.wiley.com/journal/20755597 ↗
http://ieeexplore.ieee.org/servlet/opac?punumber=7479413 ↗
http://ieeexplore.ieee.org/Xplore/home.jsp ↗ - DOI:
- 10.1049/cje.2016.06.039 ↗
- Languages:
- English
- ISSNs:
- 1022-4653
- Deposit Type:
- Legaldeposit
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- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 3180.317180
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- 16492.xml