On‐Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time. Issue 1 (1st January 2016)

• Record Type: Journal Article
• Authors: Wang, Fei; Wang, Da; Yang, Haigang; Xie, Xianghui; Fan, Dongrui
• Is Part Of: Chinese journal of electronics. Volume 25:Issue 1(2016)
• Page Start: 64
• Page End: 70
• Publication Date: 2016-01-01
• Subjects: FPGA test -- Test configuration bitstream -- Design‐for‐testability; field programmable gate arrays -- integrated circuit manufacture -- integrated circuit testing; on‐chip generating FPGA test -- manufacturing test time reduction -- FPGA manufacturing test time -- test configuration bitstreams; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2016.01.010
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : Statistics shows that over 95% of FPGA manufacturing test time is spent on loading test configuration bitstreams. Reducing the test time that spent on loading test configuration bitstreams could significantly reduce FPGA test time. A new approach which can significantly reduce the FPGA test time is presented. Experimental results show that the proposed technique can at least reduce the configuration loading time by 96%, while getting 100% test coverage with less than 1.2% hardware overhead.