A 14b 250MSps Pipelined ADC with Digital Self‐calibration in 0.18µm CMOS Process. Issue 3 (1st May 2018) - Liu, Haitao; Wu, Junjie; Zhang, Lizheng; Deng, Qing; Sun, Jie
Abstract : A 14‐bit pipelined Analog‐to‐digital converter (ADC) with a single‐side digital self‐calibration in a 0.18m CMOS process is presented. The single‐side foreground digital self‐calibration is introduced to reduce the nonlinearity caused by capacitor mismatches. The ADC has a front‐end Sample‐and‐hold (SH) circuit, followed by 13 1.5bit/stage sub‐ADC and 2bit flash ADC at last. Test results show that, with a 140MHz input and 200MHz sampling rate, the SIAND is improved from 59dB to 66dB and SFDR is improved from 62dBc to 82dBc with the digital calibration. The measured SFDR reaches 77dBc even at 250MSps after calibration. The total power dissipation is 398mW at 250MSps including the parallel Low voltage differential signal (LVDS) output drivers.