A High‐Performance RSA Coprocessor Based on Half‐Carry‐Save and Dual‐Core MAC Architecture. Issue 1 (1st January 2018)

• Record Type: Journal Article
• Authors: Ding, Yanyu; Hu, Jianguo; Wang, Deming; Tan, Hongzhou
• Is Part Of: Chinese journal of electronics. Volume 27:Issue 1(2018)
• Page Start: 70
• Page End: 75
• Publication Date: 2018-01-01
• Subjects: RSA coprocessor -- Montgomery multiplication -- Half‐carry‐save -- Dual‐core MAC; coprocessors -- low‐power electronics; high‐performance RSA coprocessor -- half‐carry‐save dual‐core MAC architecture -- fast half‐carry‐save Montgomery modular multiplication algorithm -- high‐speed dual‐core multiplier accumulator architecture -- low‐power optimization schemes; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2017.11.013
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : This research focuses on the methods to improve the throughput and lower the power for low cost RSA coprocessors. We proposed the following optimized methods: 1. A fast half‐carry‐save Montgomery modular multiplication algorithm suitable for hardware implementation; 2. A high‐speed dual‐core multiplier accumulator architecture to optimize the critical path; 3. Several lowpower optimization schemes for the RSA coprocessor. The design has been implemented with TSMC 90nm technology, and the experimental results show that the critical path is 2.71ns, the power consumption is just 9.76mW and the throughput can reach 381.57kbps. Compared with relative works, our design is featured by the minimal power and the best overall performance, thus it is most suitable for applications in low‐power systems.