A 10‐bit 500‐MS/s Current Steering DAC with Improved Random Layout. Issue 1 (1st January 2020)

• Record Type: Journal Article
• Authors: Tong, Xingyuan; Wang, Chaofeng
• Is Part Of: Chinese journal of electronics. Volume 29:Issue 1(2020)
• Page Start: 73
• Page End: 81
• Publication Date: 2020-01-01
• Subjects: Digital‐to‐analog converter -- Segmented current steering -- Random layout -- Nonlinearity; binary codes -- CMOS integrated circuits -- constant current sources -- digital‐analogue conversion -- integrated circuit layout -- random processes -- sensor arrays -- temperature measurement -- temperature sensors -- thermometers; ENOB -- effective number of bits -- SFDR -- spurious free dynamic range -- INL -- integral nonlinearity -- DNL -- differential nonlinearity -- CMOS integrated circuit -- segmented current steering digital‐to‐analog converter -- improved random layout scheme -- layout plan optimization -- current source array -- segmented current steering DAC -- binary code -- thermometer code -- second‐order systematic mismatch errors -- size 0.18 mum -- power 14.3 mW -- voltage 1.8 V -- frequency 1.465 MHz -- word length 9.2 bit -- word length 10 bit -- word length 6 bit -- word length 4 bit -- voltage 1 V -- gain 65.6 dB; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2019.10.002
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : According to the segmented current steering Digital‐to‐analog converter (DAC), the influence of current mismatch and output impedance of the current array on the linearity of DAC is discussed by theoretical analysis and derivation. An optimized layout plan for the current source array randomizes all these unit current sources corresponding to each thermometer code, which can significantly reduce the fist‐order and second‐order systematic mismatch errors in the current source array, and improve the linearity performance of DAC. With the segmented structure of 6 bit thermometer code and 4 bit binary code, a 10‐bit DAC is realized in a 0.18mm CMOS by using the above layout plan. The active area of this DAC is 620μm × 340μm. Operated at 1V digital supply and 1.8V analog supply, with 500 MS/s sampling rate, the measured power consumption of this DAC is 14.3mW. The measurement results show that the Differential nonlinearity (DNL) and the Integral nonlinearity (INL) of the DAC with this random layout scheme are 0.71 LSB and 1.02 LSB. With 500 MS/s sampling rate and 1.465MHz input frequency, the Spurious free dynamic range (SFDR) and the Effective number of bits (ENOB) are 65.6dB and 9.2 bit, respectively.