Efficient Multi‐rate Encoder of QC‐LDPC Codes Based on FPGA for WIMAX Standard. Issue 2 (1st March 2017)

• Record Type: Journal Article
• Authors: Wang, Xiumin; Ge, Tingting; Li, Jun; Su, Chen; Hong, Fangfei
• Is Part Of: Chinese journal of electronics. Volume 26:Issue 2(2017)
• Page Start: 250
• Page End: 255
• Publication Date: 2017-03-01
• Subjects: Encoder -- Multi‐rate -- FPGA -- Dual Diagonal -- WIMAX; encoding -- field programmable gate arrays -- matrix algebra -- parity check codes -- WiMax; QC‐LDPC codes -- FPGA -- WIMAX standard -- ALT form -- approximately lower triangular form -- memory bits -- storage compression -- bidirectional operation -- MVM units -- parallel matrix‐vector multiplication units -- parity matrices -- common dual‐diagonal structure -- IEEE 802.16e LDPC codes -- multi‐rate encoder -- frequency 117 MHz; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2017.01.006
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : An efficient multi‐rate encoder for IEEE 802.16e LDPC codes which outperforms current single rate encoders with acceptable hardware consumption and efficient memory consumption is proposed. This design utilizes the common dual‐diagonal structure in parity matrices to avoid the inverse matrix operation which requires extensive computations. Parallel Matrix‐vector multiplication (MVM) units, bidirectional operation and storage compression are applied to this multi‐rate encoder to increase the encoding speed and significantly reduce the quantity of memory bits required. The proposed encoding architecture also contributes to the design of multi‐rate encoders whose parity matrices are dual‐diagonally structured and have an Approximately lower triangular (ALT) form, such as in IEEE 802.11n and IEEE 802.22. Simulation results verified that the proposed encoder can efficiently work for all code rates specified in WIMAX standard. With a maximum clock frequency of 117 MHz, the encoder achieves 3 to 10 times higher throughput than prior works. The proposed encoder is capable to switch among six rates by adjusting the input parameter and it achieves the throughput up to 1Gbps.