A Low‐Power Low‐Cost 780MHz CMOS FSK Receiver for Short‐Range Wireless Communication. Issue 2 (1st March 2016)

• Record Type: Journal Article
• Authors: Yin, Yadong; Yang, Yuanting; Zhang, Lihong
• Is Part Of: Chinese journal of electronics. Volume 25:Issue 2(2016)
• Page Start: 220
• Page End: 226
• Publication Date: 2016-03-01
• Subjects: CMOS integrated circuit -- Current reused -- Frequency offset tolerance -- Frequency shift keying (FSK) demodulation -- Low power -- Receiver; active filters -- circuit tuning -- CMOS integrated circuits -- frequency shift keying -- low‐power electronics -- radio receivers -- UHF integrated circuits -- UHF mixers -- UHF power amplifiers; low‐power low‐cost CMOS FSK receiver -- short‐range wireless communication -- frequency shift keying -- current‐reused low‐power amplifier -- current‐reused LNA -- single‐balance passive mixer -- current consumption -- 3rd‐order active‐RC complex filter -- reconfigurable bandwidth -- process‐voltage‐temperature variation -- replica‐circuit master‐slave automatic tuning circuit -- PVT variation -- discrete‐time differentiator -- demodulator -- frequency offset -- intermediate frequency -- frequency 780 MHz -- size 0.18 mum -- frequency 1.5 MHz to 3.7 MHz -- current 4.7 mA -- voltage 1.8 V; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2016.03.005
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : This paper presents a low‐power low‐cost 780MHz CMOS Frequency shift keying (FSK) receiver for short‐range wireless communication. A current‐reused Low power amplifier (LNA) and a single‐balance passive mixer are employed to cut down the current consumption of the RF frontend in receiver. A 3 rd ‐order active‐RC complex filter with reconfigurable bandwidth is implemented and a novel automatic tuning circuit is used in the filter to eliminate the negative effect of the Process, voltage, temperature (PVT) variations. A novel replica‐circuit master‐slave automatic tuning circuit and a discrete‐time differentiator are employed in demodulator to keep the demodulation performances from the PVT variations and the frequency offset of Intermediate frequency (IF). The receiver is fabricated in 0.18µm CMOS and occupies a chip area of about 0.97mm 2 . It can achieve a sensitivity of −83.7dBm and a tolerance of IF range from 1.5MHz to 3.7MHz with a 4.7mA current consumption under a 1.8V supply.