Automated verification of input completeness for NCL circuits. Issue 20 (1st October 2018)

• Record Type: Journal Article
• Authors: Le, S.; Srinivasan, S.K.; Smith, S.C.
• Is Part Of: Electronics letters. Volume 54:Issue 20(2018)
• Page Start: 1158
• Page End: 1160
• Publication Date: 2018-10-01
• Subjects: asynchronous circuits -- logic design -- formal verification; input completeness -- NCL circuit -- automated formal verification approach -- NULL Convention Logic circuits -- extreme environments -- circuit timing; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2018.6068
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An automated formal verification approach for ensuring input completeness of NULL Convention Logic (NCL) circuits is proposed. NCL circuits have the benefit that they can operate in extreme environments where traditional synchronous circuits fail due to significant fluctuations in circuit timing. Input completeness is a critical property to ensure correct functioning of NCL circuits in extreme environments and therefore is required to be verified. Note that an NCL circuit can be functionally correct and still not be input complete, which could cause the circuit to operate correctly under normal conditions, but malfunction only when the circuit timing is substantially changed (e.g. operating in a very hot or cold environment such as outer space).