K‐band CMOS frequency doubler with high fundamental rejection. Issue 17 (1st August 2014) - Wang, Sen
Abstract : The design of a frequency doubler with current‐reuse and fundamental rejection topology is presented. The frequency doubler is fabricated by a standard 0.18 μm CMOS process with a chip size of 0.57 mm 2 . The DC power consumption is 13.9 mW. In addition, the measured conversion gain is between –4.4 and –5.24 dB from 10 to 12 GHz input frequency. With the proposed active notch filter in the cascode stage of the doubler, a superior fundamental rejection is obtained. The measured fundamental rejection is between 32.4 and 53.8 dB.