Improved binary‐weighted split‐capacitive‐array DAC for high‐resolution SAR ADCs. Issue 17 (1st August 2014)

• Record Type: Journal Article
• Authors: Li, Y.; Lian, Y.
• Is Part Of: Electronics letters. Volume 50:Issue 17(2014)
• Page Start: 1194
• Page End: 1195
• Publication Date: 2014-08-01
• Subjects: digital‐analogue conversion -- analogue‐digital conversion -- capacitors -- power consumption; improved binary‐weighted split‐capacitive‐array DAC -- high‐resolution SAR ADCs -- digital‐to‐analog converter -- most significant bit -- MSB sub‐array -- switching power consumption -- CBW -- attenuation capacitor -- BWA -- power dissipation -- analog‐to‐digital converter dynamic performance -- optimum segmentation degree -- unit capacitor -- word length 12 bit; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2014.1752
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An improved split‐capacitive‐array digital‐to‐analogue converter (DAC) with an optimised segmentation degree (i.e. the number of bits in the most significant bit (MSB) sub‐array) is proposed to reduce the area, the switching power consumption and improve the linearity compared to a conventional binary‐weighted (CBW) capacitive‐array DAC and a conventional binary‐weighted split‐capacitive‐array with an attenuation capacitor (BWA) DAC. The presented analysis considers the area and the power dissipation from the DAC as well as the analogue‐to‐digital converter's (ADC's) dynamic performance to determine the optimum segmentation degree for the proposed split‐capacitive‐array DAC and the BWA DAC. Using the minimum matching requirement for the unit capacitor in a 12‐bit CBW DAC, the proposed split‐capacitive‐array DAC with an MSB:LSB = 8:4 segmentation reduces the input capacitance by 2× and reduces the switching power by 15× compared to the 12‐bit CBW DAC. It also improves the ADC's dynamic performance and reduces the switching power by 3.75× compared to the conventional 12‐bit BWA DAC with an MSB:LSB = 10:2 segmentation.