CMOS low‐power bandwidth‐improved derivative superposition mixer using parasitic NPN BJTs. Issue 25 (1st December 2013)

• Record Type: Journal Article
• Authors: Wang, Keping; Lei, Xuemei
• Is Part Of: Electronics letters. Volume 49:Issue 25(2013)
• Page Start: 1605
• Page End: 1607
• Publication Date: 2013-12-01
• Subjects: bipolar transistors -- CMOS integrated circuits -- microwave mixers; voltage 1 V -- power 3.8 mW -- bandwidth 0.5 GHz to 6 GHz -- gain 7.2 dB -- size 90 nm -- third order input interception point -- parasitic capacitance -- bipolar junction transistor -- saturated NMOS pseudodifferential transistor -- parasitic NPN BJT -- CMOS low power bandwidth improved derivative superposition mixer; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.2804
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A low‐power bandwidth‐improved derivative superposition (DS) mixer in a standard 90 nm CMOS technology is analysed in depth. The negative g m ″ in saturated NMOS pseudo‐differential transistor is compensated by the positive g m ″ in the parasitic NPN bipolar junction transistor. Compared with the traditional DS mixer using the dual‐NMOS method, the proposed DS mixer shows a wider bandwidth owing to the lower parasitic capacitance at the base. The maximum conversion gain of the DS mixer is 7.2 dB with the 1 dB frequency bandwidth from 0.5 to 6 GHz. Compared with the Gilbert‐type mixer, the third‐order input interception point (IIP3 ) is improved by about 7.5 dB. The DS mixer consumes a DC power of 3.8 mW under 1 V supply.