Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers. Issue 10 (1st May 2015)

• Record Type: Journal Article
• Authors: Lu, Wenjuan; Peng, Chunyu; Tao, Youwu; Li, Zhengping
• Is Part Of: Electronics letters. Volume 51:Issue 10(2015)
• Page Start: 742
• Page End: 743
• Publication Date: 2015-05-01
• Subjects: SRAM chips -- amplifiers -- timing; replica bitline technique -- RBL technique -- sense amplifier enable timing -- SAE timing -- four‐fold replica cells -- cycle time -- TSMC 65 nm technology -- SRAM sense amplifiers -- variation‐tolerant timing generation scheme -- voltage 0.8 V -- size 65 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.0574
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An efficient replica bitline (RBL) technique for reducing the variation of sense amplifier enable (SAE) timing is proposed. Both RBLs and four‐fold replica cells compared with the conventional RBL technique are utilised to favour the desired operations. Simulation results show that the standard deviation of SAE can be suppressed by 44.25% and the cycle time is also reduced by ∼30% at a 0.8 V supply voltage in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that of the conventional RBL scheme.