High reliability sensing circuit for deep submicron spin transfer torque magnetic random access memory. Issue 20 (1st September 2013)

• Record Type: Journal Article
• Authors: Kang, Wang; Zhao, Weisheng; Klein, J.‐O.; Zhang, Youguang; Chappert, C.; Ravelosona, D.
• Is Part Of: Electronics letters. Volume 49:Issue 20(2013)
• Page Start: 1283
• Page End: 1285
• Publication Date: 2013-09-01
• Subjects: CMOS memory circuits -- magnetic tunnelling -- Monte Carlo methods -- random‐access storage -- semiconductor device reliability; high reliability sensing circuit -- deep submicron spin transfer torque magnetic random access memory -- triple‐stage sensing operation -- deep submicron nodes -- bit‐line voltage -- predefined small bias voltage -- STMicroelectronics CMOS design kit -- STT‐MTJ compact model -- Monte Carlo simulations; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.2319
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A high reliability offset‐tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT‐MTJ) memory. This circuit, using a triple‐stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bit‐line voltage to a predefined small bias voltage to avoid any read disturbance during the sensing operations. By using the STMicroelectronics CMOS 40 nm design kit and a precise STT‐MTJ compact model, Monte Carlo simulations have been carried out to evaluate its sensing performance.