Highly linear current‐controlled delay unit. Issue 15 (3rd July 2015)

• Record Type: Journal Article
• Authors: Ahamed, M.R.; Sandhu, T.S.; El‐Sankary, K.
• Is Part Of: Electronics letters. Volume 51:Issue 15(2015)
• Page Start: 1157
• Page End: 1159
• Publication Date: 2015-07-03
• Subjects: invertors -- Monte Carlo methods -- CMOS integrated circuits -- time‐digital conversion -- delay circuits -- active networks; highly linear current‐controlled delay unit -- CCDU -- input clock edge -- directly proportional input‐output relation -- current‐starved inverter -- CSI -- THD -- CMOS -- analogue‐time‐digital ADC -- ENOB -- Monte Carlo -- current 180 nA -- size 65 nm -- power 0.74 muW; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.1836
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A highly linear current‐controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/output relation compared with an inversely proportional one in the traditional current‐starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue‐time‐digital ADC is simulated using the proposed CCDU as a front‐end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.