Optimised decoding of odd‐weight single error correction double error detection codes with 64 bits. Issue 25 (1st December 2013)

• Record Type: Journal Article
• Authors: Reviriego, P.; Pontarelli, S.; Maestro, J.A.
• Is Part Of: Electronics letters. Volume 49:Issue 25(2013)
• Page Start: 1617
• Page End: 1618
• Publication Date: 2013-12-01
• Subjects: decoding -- delays -- error correction codes -- error detection codes; optimised decoding -- odd‐weight single error correction double error detection codes -- SEC‐DED -- 64 bits -- parity check matrix -- odd‐weight columns -- even weight syndrome -- decoding complexity -- decoder circuitry area -- word length 64 bit; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.2897
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Error correction codes are commonly used in memories to ensure that data are not corrupted. Single error correction double error detection (SEC‐DED) codes are among the most widely used codes to protect memories. One common technique to implement SEC‐DED codes is to construct a parity check matrix with odd‐weight columns. This ensures that double errors have an even weight syndrome and therefore are not confused with single errors thus providing the DED feature. Recently, a technique that reduces the decoding complexity for odd‐weight SEC‐DED codes has been proposed. This technique can be used only for small data block sizes being the practical limit 32 bits. However, memories with 64 bits are commonly found in modern computing systems. Therefore, it would be advantageous to also reduce the decoding complexity for larger block sizes. A scheme to optimise the decoding of odd‐weight SEC‐DED codes with block sizes of 64 bits is presented and evaluated. The results show that the new scheme can provide significant reductions in the decoder circuitry area and delay.