Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process. Issue 5 (1st March 2017)

• Record Type: Journal Article
• Authors: Kim, E.; Oh, T.
• Is Part Of: Electronics letters. Volume 53:Issue 5(2017)
• Page Start: 308
• Page End: 310
• Publication Date: 2017-03-01
• Subjects: CMOS integrated circuits; single‐ended dual‐mode near‐ground transmitter IO driver -- CMOS process -- smart dual‐mode IO driver -- termination scheme -- low‐speed data transmission -- high‐speed data transmission -- near‐ground signalling -- pre‐emphasis weight -- FIR tap control -- FR4 channel -- proto‐type 2 channel driver -- size 45 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2016.4290
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A smart dual‐mode IO driver and termination scheme is proposed and power is efficiently consumed for both low‐speed data transmission under 500 Mbit/s and high‐speed data transmission up to 3.4 Gbit/s. During high speed data transmission, the driver uses near‐ground signalling and pre‐emphasis weight can be controlled for inter symbol interference (ISI) mitigation. The measured eye shows 17.8% vertically and 19.5% horizontally with finite impulse response (FIR) tap control for 15.75″ FR4 channel. The proto‐type 2 channel single‐ended driver has been implemented in 45 nm CMOS process and occupies 0.022 mm 2 chip area.