Two‐step continuous‐time incremental sigma–delta ADC. Issue 12 (1st June 2013) - Tao, S.; Rodriguez, S.; Rusu, A.
Abstract : A two‐step continuous‐time (CT) incremental sigma–delta (IΣΔ) ADC, which enhances the performance of conventional CT IΣΔ ADCs, is proposed. By pipelining two second‐order CT IΣΔ ADCs, the proposed two‐step architecture can achieve high resolution without sacrificing the conversion rate. Compared to other alternatives, the two‐step CT IΣΔ ADC exhibits the freedom of adjusting its accuracy and speed independently while featuring quite relaxed circuit specifications.